1. Field of the Invention
The invention relates to a clock generating device, a method thereof, and a computer system using the same and, more particularly, to a device for tuning a frequency of an output clock signal according to a voltage identification definition (VID) of a central processing unit (CPU).
2. Description of the Related Art
Nowadays, to improve a performance and service time of products in an information technology (IT) industry, a demand for a power standard gradually become higher. All advance RISC machine (ARM) processors, Intel processors, and AMD processors are designed with a dynamic voltage frequency scaling (DVFS) function to dynamically reduce an operating frequency and an operating voltage of the computer system when the computer system is idle or does not need heavy computation.
FIG. 1 is a block diagram showing a conventional computer system. A CPU 120 and a chipset 130 receive a clock signal HCLK generated by a clock generator 110 to serve as a basic clock at which the CPU 120 and the chipset 130 operate. The frequency identification definition (FID) and a VID generated by the CPU 120 are changed along with an operating mode to dynamically adjust the operating frequency and the operating voltage to reduce power consumption. When a computer system 100 does not need to consume a great deal of power on heavy computation, a phase lock loop (PLL) in the CPU 120 internally adjusts the frequency of the received clock signal HCLK or an intrinsic frequency dividing ratio to reduce the operating frequency of the CPU 120. Furthermore, the CPU 120 also generates the VID to a voltage regulator module (VRM) 140 according to the operating mode to allow the VRM 140 to reduce an operating voltage Vcore of the CPU 120 according to the VID.
However, the above voltage and frequency dynamic adjusting mechanism is used for adjusting the operating frequency and the operating voltage of the CPU 120. Thus, operating frequencies of the chipset 130 and a dynamic random access memory (DRAM) 150 connected with the CPU 120 via a front side bus (FSB) keeps original. As a result, the computer system 100 still has unnecessary power consumption when it is idle or does not need heavy computations.